1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, such as miniature MOS transistors, EPROMs, EEPROMs and flash-type EEPROMs, that use a thin oxide film as a gate insulating film.
2. Description of the Related Art
FIG. 2 shows the structure in cross section of a memory cell of an ultraviolet erasable EPROM manufactured according to the prior art. This memory cell has a gate insulation film 102 in the form of a thin oxide film formed over the surface of a semiconductor substrate 101. A first layer polysilicon gate electrode 103, which will form a floating gate, is deposited on the gate insulation film 102 by a chemical vapor deposition (CVD) method. The polysilicon electrode 103 is subjected to thermal oxidation to form an inter-polysilicon-layer insulation film 104. Further, on this insulation film 104, a second layer polysilicon gate electrode 105, which will work as a control gate, is deposited by a CVD method. Then, the floating gate electrode 103, the inter-polysilicon-layer 104 and the control gate electrode 105 are simultaneously etched using photoresist as a mask. As the last step, with the polysilicon gate electrodes used as an implantation mask, arsenic is implanted into the substrate to form a self-aligned source region 106 and a self-aligned drain region 107.
The above-identified self-aligning ion implantation, which is performed during the process of forming the source and drain regions in MOS transistors and memory cells that use a thin oxide film as a gate insulation film, causes damage to the structure of the thin oxide film directly below the polysilicon gate electrode edge. That is, flaws are introduced into the structure of the thin oxide film. In MOS transistors, a leakage current flows through this structural flaw between the gate electrode and the source and drain, rendering the transistors unable to function correctly.
In the case of memory cells, the ion implantation damage causes the following problem: when a positive high voltage is applied to the source or drain region, charges accumulated in the floating gate as information will flow out through the flaw as a leakage current, thus making nonvolatile storage of information impossible.